RM0046 Voltage Regulators and Power Supplies
Doc ID 16912 Rev 5 837/936
An LVD_DIG in the regulator senses the HPREG output. It provides V
MLVDDOK_H
and
V
MLVDOK_L
as active high signals.
The reference voltage used for all LVDs is trimmed for LVD_DIG using the bits LP[4:7].
Therefore, during the pre-trimming period, LVD_DIG exhibits higher thresholds, whereas
post trimming, the thresholds come in the desired range. The trimming bits are provided by
SSCM device option bits, which are updated during the reset phase (RGM reset phase 2)
only. Power-down pins are provided for LVDs. When LVDs are powered down, their outputs
are pulled high. LVDs are not controllable by the user. The only option is the possibility to
mask LVD_MAIN5 using the mask bit (5V_LVD_MASK)
in the VREG_CTL register.
POR is required to initialize the device during supply rise. POR works only on the rising
edge of main supply. To ensure its functioning during the following rising edge of the supply,
it is reset by the output of the LVD_MAIN block when main supply reaches below the lower
voltage threshold of the LVD_MAIN.
POR is asserted on power-up when V
DD
supply is above V
PORUP
minimum (refer to
datasheet for details). It is released only after V
DD
supply is above V
PORH
(refer to datasheet
for details). V
DD
above V
PORH
ensures power management module including internal LVDs
modules are fully functional.
34.1.3 VREG digital interface
The voltage regulator digital interface provides the temporization delay at initial power-up
and at exit from low-power modes. A signal, indicating that Low Power domain is powered, is
used at power-up to release reset to temporization counter. On completion of the delay
counter, a end-of-count signal is released, it is gated with an other signal indicating main
domain voltage fine in order to release the VREGOK signal. This is used by RGM to release
the reset to the device.
The VREG digital interface also holds control register to mask 5 V LVD status coming from
the voltage regulator at the power-up.