RM0046 System Integration Unit Lite (SIUL)
Doc ID 16912 Rev 5 257/936
Note: If both the IREER.IREE and IFEER.IFEE bits are cleared for the same interrupt source, the
interrupt status flag for the corresponding external interrupt will never be set.
Interrupt Filter Enable Register (IFER)
This register enables a digital filter counter on the corresponding interrupt pads to filter out
glitches on the inputs.
Pad Configuration Registers (PCR[0:71])
The Pad Configuration Registers allow configuration of the static electrical and functional
characteristics associated with I/O pads. Each PCR controls the characteristics of a single
pad.
Note: 16/32-bit access is supported for the PCR[0:71] registers.
Figure 104. Interrupt Filter Enable Register (IFER)
Address:
Base + 0x0030 Access: User read/write
0123456789101112131415
R
IFE[24:16]
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IFE[15:0]
W
Reset0000000000000000
Table 97. IFER field descriptions
Field Description
IFEn
Enable digital glitch filter on the interrupt pad input.
0: Filter disabled
1:Filter enabled
Figure 105. Pad Configuration Registers 0–71 (PCR[0:71])
Address:
Base + 0x0040 (PCR0)
...
Base + 0x00CE (PCR71) 72 registers
Access: User read/write
0123456789101112131415
R0
SMC APC
0
PA[1:0] OBE IBE
00
ODE
00
SRC WPE WPS
W
Reset
(1)
0000000000000000
1. See Table 99.
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