ST SPC560P34 - Table 151. LML and NVLML Field Descriptions; Figure 154. Low;MID Address Space Block Locking Register (LML); Figure 155. Non-Volatile Low;MID Address Space Block Locking Register (NVLML)

RM0046 Flash Memory
Doc ID 16912 Rev 5 347/936
In the code Flash module, the LML register has a related Non-Volatile Low/Mid Address
Space Block Locking register (NVLML) located in TestFlash that contains the default reset
value for LML. The NVLML register is read during the reset phase of the Flash module and
loaded into the LML. The reset value is 0x00XX_XXXX, initially determined by the NVLML
value from test sector.
Non-Volatile Low/Mid Address Space Block Locking register (NVLML)
The NVLML register is a 64-bit register, the 32 most significant bits of which (bits 63:32) are
“don’t care” bits that are eventually used to manage ECC codes. Identical NVLML registers
are provided in the code Flash and the data Flash blocks.
Figure 154. Low/Mid Address Space Block Locking register (LML)
Address: Base + 0x0004 Access: User read/write
0123456789101112131415
RLME0000000 000
TSLK
0 0 0 0
W
Reset00000000000x00xx
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
LLK
15
LLK
14
LLK
13
LLK
12
LLK
11
LLK
10
LLK
9
LLK
8
LLK
7
LLK
6
LLK
5
LLK
4
LLK
3
LLK
2
LLK
1
LLK
0
W
Resetxxxxxxxxxxxxxxxx
Figure 155. Non-Volatile Low/Mid Address Space Block Locking register (NVLML)
Address: Base + 0x40_3DE8 Access: User read/write
0123456789101112131415
R00000000 000
TSLK
0 0 0 0
W
Reset00000000000x00xx
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
LLK
15
LLK
14
LLK
13
LLK
12
LLK
11
LLK
10
LLK
9
LLK
8
LLK
7
LLK
6
LLK
5
LLK
4
LLK
3
LLK
2
LLK
1
LLK
0
W
Resetxxxxxxxxxxxxxxxx
Table 151. LML and NVLML field descriptions
Field Description
LME
(1)
0
Low/Mid Address Space Block Enable
This bit enables the Lock registers (TSLK and LLK[15:0]) to be set or cleared by registers writes.
This bit is a status bit only. The method to set this bit is to write a password, and if the password
matches, the LME bit is set to reflect the status of enabled, and is enabled until a reset operation
occurs. For LME the password 0xA1A11111 must be written to the LML register.
0 Low Address Locks are disabled: TSLK and LLK[15:0] cannot be written.
1 Low Address Locks are enabled: TSLK and LLK[15:0] can be written.
1:10
Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.