ST SPC560P34 - Figure 229. TX FIFO Pointers and Counter

RM0046 Deserial Serial Peripheral Interface (DSPI)
Doc ID 16912 Rev 5 483/936
Figure 229 illustrates the concept of first-in and last-in FIFO entries along with the FIFO
counter.
Figure 229. TX FIFO pointers and counter
Address calculation for first-in entry and last-in entry in TX FIFO
The memory address of the first-in entry in the TX FIFO is computed by the following
equation:
Equation 27
The memory address of the last-in entry in the TX FIFO is computed by the following
equation:
Equation 28
where:
TXFIFO base = base address of transmit FIFO
TXCTR = transmit FIFO counter
TXNXTPTR = transmit next pointer
TX FIFO depth = transmit FIFO depth (depth is 5)
Address calculation for first-in entry and last-in entry in RX FIFO
The memory address of the first-in entry in the RX FIFO is computed by the following
equation:
Entry C
Entry A (first in)
– 1
Entry B
Entry D (last in)
TX FIFO base
Push TX FIFO
TX FIFO counter
Shift register SOUT
register
Transmit next
data pointer
–
–
–
–
+ 1
(TXNXTPTR)
First-in entry address = TXFIFO base + 4 (TXNXTPTR)
Last-in entry address = TXFIFO base + 4 × [(TXCTR + TXNXTPTR – 1) modulo TXFIFO depth]