RM0046 e200z0 and e200z0h Core
Doc ID 16912 Rev 5 275/936
Nexus features
The Nexus 1 module is compliant with Class 1 of the IEEE-ISTO 5001-2003 standard. The
following features are implemented:
â—Ź Program Trace via Branch Trace Messaging (BTM). Branch trace messaging displays
program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing
the development tool to interpolate what transpires between the discontinuities. Thus,
static code may be traced.
â—Ź Ownership Trace via Ownership Trace Messaging (OTM). OTM facilitates ownership
trace by providing visibility of which process ID or operating system task is activated.
An Ownership Trace Message is transmitted when a new process/task is activated,
allowing the development tool to trace ownership flow.
â—Ź Run-time access to the processor memory map via the JTAG port. This allows for
enhanced download/upload capabilities.
â—Ź Watchpoint Messaging
â—Ź Watchpoint Trigger enable of Program Trace Messaging
â—Ź Registers for Program Trace, Ownership Trace and Watchpoint Trigger control
â—Ź All features controllable and configurable via the JTAG port
12.3 Core registers and programmer’s model
This section describes the registers implemented in the e200z0 and e200z0h cores. It
includes an overview of registers defined by the Power Architecture technology, highlighting
differences in how these registers are implemented in the e200 core, and provides a
detailed description of e200-specific registers. Full descriptions of the architecture-defined
register set are provided in Power Architecture Specification.
The Power Architecture defines register-to-register operations for all computational
instructions. Source data for these instructions are accessed from the on-chip registers or
are provided as immediate values embedded in the opcode. The three-register instruction
format allows specification of a target register distinct from the two source registers, thus
preserving the original data for use by other instructions. Data is transferred between
memory and registers with explicit load and store instructions only.
Figure 118 and Figure 120 show the e200 register set, including the registers that are
accessible while in supervisor mode and the registers that are accessible in user mode. The
number to the right of the special-purpose registers (SPRs) is the decimal number used in
the instruction syntax to access the register (for example, the integer exception register
(XER) is SPR 1).
Note: e200z0 and e200z0h is a 32-bit implementation of the Power Architecture specification.
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