ST SPC560P34 - Figure 428. SWT Control Register (SWT_CR); Table 391. SWT Memory Map; Table 392. SWT_CR Field Descriptions

RM0046 Functional Safety
Doc ID 16912 Rev 5 747/936
SWT Control Register (SWT_CR)
The SWT_CR contains fields for configuring and controlling the SWT. The reset value of this
register is device specific. Some devices can be configured to automatically clear the
SWT_CR[WEN] bit during the boot process. This register is read-only if either the
SWT_CR[HLK] or SWT_CR[SLK] bits are set.
The default reset value for SWT_CR is 0xFF00_011B, corresponding to MAP1 = 1 (only
data bus access allowed), RIA = 1 (reset on invalid SWT access), SLK = 1 (soft lock),
CSL = 1 (IRC clock source for counter), FRZ = 1 (freeze on debug), WEN = 1 (watchdog
enable). This last bit is cleared when exiting ME RESET mode in case flash user option bit
31 (WATCHDOG_EN) is 0.
Table 391. SWT memory map
Offset from
SWT_BASE
0xFFF3_8000 (SWT_0)
0x8FF3_8000 (SWT_1)
Register Location
0x0000 SWT_CR—SWT Control Register on page 27-747
0x0004 SWT_IR—SWT Interrupt Register on page 27-749
0x0008 SWT_TO—SWT Time-Out register on page 27-749
0x000C SWT_WN—SWT Window Register on page 27-750
0x0010 SWT_SR—SWT Service Register on page 27-751
0x0014 SWT_CO—SWT Counter Output register on page 27-751
0x0018 SWT_SK—SWT Service Key register on page 27-752
0x001C–0x03FF Reserved
Figure 428. SWT Control Register (SWT_CR)
Address: Base + 0x0000 Access: User read/write
0123456789101112131415
R
MAP0 MAP1 MAP2 MAP3 MAP4 MAP5 MAP6 MAP7
00000 000
W
Reset1111111100000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000
KEY RIA
WND ITR HLK SLK CSL STP FRZ WEN
W
Reset0000000100011011
Table 392. SWT_CR field descriptions
Field Description
MAPn
Master Access Protection for Master n.
The platform bus master assignments are device specific.
0 Access for the master is disabled.
1 Access for the master is enabled.