Functional Safety RM0046
748/936 Doc ID 16912 Rev 5
KEY
Keyed Service Mode
0 Fixed Service Sequence, the fixed sequence 0xA602, 0xB480 is used to service the watchdog.
1 Keyed Service Mode, two pseudorandom key values are used to service the watchdog.
RIA
Reset on Invalid Access
0 Invalid access to the SWT generates a bus error.
1 Invalid access to the SWT causes a system reset if WEN = 1.
WND
Window Mode
0 Regular mode, service sequence can be done at any time.
1 Windowed mode, the service sequence is only valid when the down counter is less than the value
in the SWT_WN register.
ITR
Interrupt Then Reset
0 Generate a reset on a time-out.
1 Generate an interrupt on an initial time-out, reset on a second consecutive time-out.
HLK
Hard Lock
This bit is only cleared at reset.
0 SWT_CR, SWT_TO and SWT_WN are read/write registers if SLK = 0.
1 SWT_CR, SWT_TO and SWT_WN are read only registers.
SLK
Soft Lock
This bit is cleared by writing the unlock sequence to the service register.
0 SWT_CR, SWT_TO and SWT_WN are read/write registers if HLK = 0.
1 SWT_CR, SWT_TO and SWT_WN are read only registers.
CSL
Clock Selection
Selects the internal 16 MHz IRC oscillator clock that drives the internal timer.
CSL bit can be written.The status of the bit has no effect on counter clock selection on the device.
0 System clock. (Not applicable in SPC560P40/34).
1 Oscillator clock.
STP
Stop Mode Control
Allows the watchdog timer to be stopped when the device enters stop mode.
0 SWT counter continues to run in stop mode.
1 SWT counter is stopped in stop mode.
FRZ
Debug Mode Control
Allows the watchdog timer to be stopped when the device enters debug mode.
0 SWT counter continues to run in debug mode.
1 SWT counter is stopped in debug mode.
WEN
Watchdog Enabled
0 SWT is disabled.
1 SWT is enabled.
Table 392. SWT_CR field descriptions (continued)
Field Description
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