Interrupt Controller (INTC) RM0046
230/936 Doc ID 16912 Rev 5
However, the LIFO is only 14 entries deep. An entry for a priority of 0 is not needed because
of how pushing onto a full LIFO and popping an empty LIFO are treated. If the LIFO is
pushed 15 or more times than it is popped, the priorities first pushed are overwritten. A
priority of 0 would be an overwritten priority. However, the LIFO will pop 0s if it is popped
more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is
regenerated with the popping of an empty LIFO.
The LIFO is not memory mapped.
9.6.3 Handshaking with processor
Software vector mode handshaking
This section describes handshaking in software vector mode.
Acknowledging interrupt request to processor
A timing diagram of the interrupt request and acknowledge handshaking in software vector
mode and the handshake near the end of the interrupt exception handler, is shown in
Figure 86. The INTC examines the peripheral and software configurable interrupt requests.
When it finds an asserted peripheral or software configurable interrupt request with a higher
priority than PRI in the associated INTC_CPR, it asserts the interrupt request to the
processor. The INTVEC field in the associated INTC_IACKR is updated with the preempting
interrupt request’s vector when the interrupt request to the processor is asserted. The
INTVEC field retains that value until the next time the interrupt request to the processor is
asserted. The rest of handshaking process is described in Section , “Software vector mode.
”
End of interrupt exception handler
Before the interrupt exception handling completes, INTC end-of-interrupt register
(INTC_EOIR) must be written.When written, the associated LIFO is popped so the
preempted priority is restored into PRI of the INTC_CPR. Before it is written, the peripheral
or software configurable flag bit must be cleared so that the peripheral or software
configurable interrupt request is negated.
Note: To ensure proper operation across all eSys MCUs, execute an
MBAR or MSYNC instruction
between the access to clear the flag bit and the write to the INTC_EOIR.
When returning from the preemption, the INTC does not search for the peripheral or
software settable interrupt request whose ISR was preempted. Depending on how much the
ISR progressed, that interrupt request may no longer even be asserted. When PRI in
INTC_CPR is lowered to the priority of the preempted ISR, the interrupt request for the
preempted ISR or any other asserted peripheral or software settable interrupt request at or
below that priority will not cause a preemption. Instead, after the restoration of the
preempted context, the processor will return to the instruction address that it was to next
execute before it was preempted. This next instruction is part of the preempted ISR or the
interrupt exception handler’s prolog or epilog.
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