RM0046 Interrupt Controller (INTC)
Doc ID 16912 Rev 5 229/936
any asserted peripheral or software configurable interrupt request is higher than the current
priority for a given processor, then the interrupt request to the processor is asserted. Also, a
unique vector for the preempting peripheral or software settable interrupt request is
generated for INTC interrupt acknowledge register (INTC_IACKR), and if in hardware vector
mode, for the interrupt vector provided to the processor.
Priority arbitrator subblock
The priority arbitrator subblock for each processor compares all the priorities of all of the
asserted interrupt requests assigned to that processor, both peripheral and software
configurable. The output of the priority arbitrator subblock is the highest of those priorities
assigned to a given processor. Also, any interrupt requests that have this highest priority are
output as asserted interrupt requests to the associated request selector subblock.
Request selector subblock
If only one interrupt request from the associated priority arbitrator subblock is asserted, then
it is passed as asserted to the associated vector encoder subblock. If multiple interrupt
requests from the associated priority arbitrator subblock are asserted, only the one with the
lowest vector passes as asserted to the associated vector encoder subblock. The lower
vector is chosen regardless of the time order of the assertions of the peripheral or software
configurable interrupt requests.
Vector encoder subblock
The vector encoder subblock generates the unique 9-bit vector for the asserted interrupt
request from the request selector subblock for the associated processor.
Priority comparator subblock
The priority comparator submodule compares the highest priority output from the priority
arbitrator submodule with PRI in INTC_CPR. If the priority comparator submodule detects
that this highest priority is higher than the current priority, then it asserts the interrupt
request to the processor. This interrupt request to the processor asserts whether this
highest priority is raised above the value of PRI in INTC_CPR or the PRI value in
INTC_CPR is lowered below this highest priority. This highest priority then becomes the new
priority that will be written to PRI in INTC_CPR when the interrupt request to the processor
is acknowledged. Interrupt requests whose PRIn in INTC_PSRn are zero will not cause a
preemption because their PRIn will not be higher than PRI in INTC_CPR.
Last-in first-out (LIFO)
The LIFO stores the preempted PRI values from the INTC_CPR. Therefore, because these
priorities are stacked within the INTC, if interrupts need to be enabled during the ISR, at the
beginning of the interrupt exception handler the PRI value in the INTC_CPR does not need
to be loaded from the INTC_CPR and stored onto the context stack. Likewise at the end of
the interrupt exception handler, the priority does not need to be loaded from the context
stack and stored into the INTC_CPR.
The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in
software vector mode or the interrupt acknowledge signal from the processor is asserted in
hardware vector mode. The priority is popped into PRI in the INTC_CPR whenever the
INTC_EOIR is written.
Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR equal
to 15 will not be preempted. Therefore, the LIFO supports the stacking of 15 priorities.
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