ST SPC560P34 - Table 458. DAC Events and Resultant Updates

Nexus Development Interface (NDI) RM0046
864/936 Doc ID 16912 Rev 5
settings of the DBSR, DSRR0 saved value, and potential updating of the ESR and MMU
MASx registers for various exception cases on back-to-back load/store class instructions.
Table 458. DAC events and Resultant Updates
1st load/store
class instruction
2nd load/store
class instruction
Result
DTLB Error, no DAC —
Take DTLB exception, no DBSR update, update MASx registers for
1st load/store class instruction. Update ESR.
DSI, no DAC —
Take DSI exception, no DBSR update, no MASx register update.
Update ESR.
DTLB Error, with
DACx
(1)
—
Take Debug exception, DBSR update setting DACx and IDE,
DAC_OFST not set. No MASx register update for 1st load/store class
instruction. DSRR0 points to 1st load/store class instruction. No ESR
update.
DSI, with DACx
(1)
—
Take Debug exception, DBSR update setting DACx and IDE,
DAC_OFST not set. DSRR0 points to 1st load/store class instruction.
No MASx register update. No ESR update.
DACx —
Take Debug exception, DBSR update setting DACx, DAC_OFST not
set. DSRR0 points to 2nd load/store class instruction. No MASx
register update. No ESR update.
DVC DACx No exceptions
Take Debug exception, DBSR update setting DACx, DAC_OFST set
to 2’b01. DSRR0 points to instruction after 2nd load/store class
instruction. No MASx register update. No ESR update.
DVC DACx DTLB Error, no DAC
Take Debug exception, DBSR update setting DACx, DAC_OFST not
set. DSRR0 points to 2nd load/store class instruction. No MASx
register update. No ESR update. No debug counter updates for 2nd
ld/st instruction.
Note: in this case the 2nd ld/st exception is masked. This
behavior is implementation dependent and may differ on other
CPUs.
DVC DACx DSI, no DAC
Take Debug exception, DBSR update setting DACx, DAC_OFST not
set. DSRR0 points to 2nd load/store class instruction. No MASx
register update. No ESR update. No debug counter updates for 2nd
ld/st instruction.
Note: in this case the 2nd ld/st exception is masked. This
behavior is implementation dependent and may differ on other
CPUs.
DVC DACx
DTLB Error, with
DACy
(1)
Take Debug exception, DBSR update setting DACx. DAC_OFST not
set. DSRR0 points to 2nd load/store class instruction. No MASx
register update. No ESR update. No debug counter update occurs
for the 2nd ld/st.
Note: in this case the 2nd ld/st exception is masked. This
behavior is implementation dependent and may differ on other
CPUs.