RM0046 Interrupt Controller (INTC)
Doc ID 16912 Rev 5 239/936
Proper setting of interrupt request priority
Whether an interrupt request negates outside its own ISR due to the side effect of an ISR
execution or the intentional clearing a flag bit, the priorities of the peripheral or software
configurable interrupt requests for these other flag bits must be selected properly. Their
PRIx values in INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR220_221) must
be selected to be at or lower than the priority of the ISR that cleared their flag bits.
Otherwise, those flag bits can cause the interrupt request to the processor to assert.
Furthermore, the clearing of these other flag bits also has the same timing relationship to
the writing to INTC_SSCIR0_3–INTC_SSCIR4_7 as the clearing of the flag bit that caused
the present ISR to be executed (see Section , “End of interrupt exception handler).
A flag bit whose enable bit or mask bit negates its peripheral interrupt request can be
cleared at any time, regardless of the peripheral interrupt request’s PRIx value in
INTC_PSRx_x.
9.7.10 Examining LIFO contents
In normal mode, the user does not need to know the contents of the LIFO. He may not even
know how deeply the LIFO is nested. However, if he wants to read the contents, such as in
debug mode, they are not memory mapped. The contents can be read by popping the LIFO
and reading the PRI field in either INTC_CPR. The code sequence is:
pop_lifo:
store to INTC_EOIR
load INTC_CPR, examine PRI, and store onto stack
if PRI is not zero or value when interrupts were enabled, branch to
pop_lifo
When the examination is complete, the LIFO can be restored using this code sequence:
push_lifo:
load stacked PRI value and store to INTC_CPR
load INTC_IACKR
if stacked PRI values are not depleted, branch to push_lifo
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