LIN Controller (LINFlex) RM0046
520/936 Doc ID 16912 Rev 5
Clock gating
The LINFlex clock can be gated from the Mode Entry module (MC_ME). In UART mode, the
LINFlex controller acknowledges a clock gating request once the data transmission and
data reception are completed, that is, once the Transmit buffer is empty and the Receive
buffer is full.
21.8.2 LIN mode
LIN mode comprises four submodes:
â—Ź Master mode
â—Ź Slave mode
â—Ź Slave mode with identifier filtering
â—Ź Slave mode with automatic resynchronization
These submodes are described in the following pages.
Master mode
In Master mode the application uses the message buffer to handle the LIN messages.
Master mode is selected when the LINCR1[MME] bit is set.
LIN header transmission
According to the LIN protocol any communication on the LIN bus is triggered by the Master
sending a header. The header is transmitted by the Master task while the data is transmitted
by the Slave task of a node.
To transmit a header with LINFlex the application must set up the identifier, the data field
length and configure the message (direction and checksum type) in the BIDR before
requesting the header transmission by setting LINCR2[HTRQ].
Data transmission (transceiver as publisher)
When the master node is publisher of the data corresponding to the identifier sent in the
header, then the slave task of the master has to send the data in the Response part of the
LIN frame. Therefore, the application must provide the data to LINFlex before requesting the
header transmission. The application stores the data in the message buffer BDR. According
to the data field length, LINFlex transmits the data and the checksum. The application uses
the BDR[CCS] bit to configure the checksum type (classic or enhanced) for each message.
If the response has been sent successfully, the LINSR[DTF] bit is set. In case of error, the
DTF flag is not set and the corresponding error flag is set in the LINESR (see Section , Error
handling).
It is possible to handle frames with a Response size larger than 8 bytes of data (extended
frames). If the data field length in the BIDR is configured with a value higher than 8 data
bytes, the LINSR[DBEF] bit is set after the first 8 bytes have been transmitted. The
application has to update the buffer BDR before resetting the DBEF bit. The transmission of
the next bytes starts when the DBEF bit is reset.
After the last data byte (or the checksum byte) has been sent, the DTF flag is set.
The direction of the message buffer is controlled by the BIDR[DIR] bit. When the application
sets this bit the response is sent by LINFlex (publisher). Resetting this bit configures the
message buffer as subscriber.
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