Crossbar Switch (XBAR) RM0046
284/936 Doc ID 16912 Rev 5
14.6.4 Slave ports
The goal of the XBAR with respect to the slave ports is to keep them 100% saturated when
masters are actively making requests. To do this the XBAR must not insert any bubbles onto
the slave bus unless absolutely necessary.
There is only one instance when the XBAR forces a bubble onto the slave bus when a
master is actively making a request. This occurs when a handoff of bus ownership occurs
and there are no wait states from the slave port. A requesting master that does not own the
slave port is granted access after a one clock delay.
14.6.5 Priority assignment
Each master port is assigned a fixed 3-bit priority level (hard-wired priority). Ta bl e 11 1
shows the priority levels assigned to each master (the lowest has highest priority).
14.6.6 Arbitration
XBAR supports only a fixed-priority comparison algorithm.
Fixed priority operation
When operating in fixed-priority arbitration mode, each master is assigned a unique priority
level in the XBAR_MPR. If two masters both request access to a slave port, the master with
the highest priority in the selected priority register gains control over the slave port.
Any time a master makes a request to a slave port, the slave port checks to see if the new
requesting master’s priority level is higher than that of the master that currently has control
over the slave port (if any). The slave port does an arbitration check at every clock edge to
ensure that the proper master (if any) has control of the slave port.
If the new requesting master’s priority level is higher than that of the master that currently
has control of the slave port, the higher priority master is granted control at the termination
of any currently pending access, assuming the pending transfer is not part of a burst
transfer.
A new requesting master must wait until the end of the fixed-length burst transfer, before it is
granted control of the slave port. But if the new requesting master’s priority level is lower
than that of the master that currently has control of the slave port, the new requesting
master is forced to wait until the master that currently has control of the slave port is finished
accessing the current slave port.
Table 111. Hardwired bus master priorities
Module
Port
Priority level
Type Number
e200z0 core–CPU instructions Master 0 7
e200z0 core—Data Master 1 6
eDMA Master 2 5
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