RM0046 Cross Triggering Unit (CTU)
Doc ID 16912 Rev 5 615/936
24.7 Interrupts and DMA requests
24.7.1 DMA support
The DMA can be used to configure the CTU registers. One DMA channel is reserved for
performing a block transfer, and the MRS can be used as an optional DMA request signal
(MRS_DMAE bit in the CTU Interrupt/DMA Register).
Note: If enabled, the DMA request on the MRS occurrence is performed only if a reload is
performed, that is, only if the GRE bit is set.
Moreover, this CTU implementation requires DMA support for reading the data from the
FIFOs. One DMA channel is available for each FIFO. Each FIFO can perform a DMA
request when the number of words stored in the FIFO reaches the threshold value.
24.7.2 CTU faults and errors
Faults and errors that could occur during the programming include:
● An MRS occurs while user is updating the double-buffered registers and the MRS_RE
bit is set.
● Receiving more than eight EVs before that the next MRS occurs in TGS sequential
mode and the SM_TO bit is set.
● A trigger event occurs during the time when the actions of the previous trigger event are
not completed (user ensures no trigger event occurs during another one is processed,
but if user makes a mistake and a trigger event occurs when another one is processed,
the incoming trigger event will be lost and an error occurs).
There are four overrun flags (one for each type of output). The general mechanism
shall be as in Figure 307.
The Trigger Handler, when a trigger event occurs, and the corresponding Ready signal
is high, presents the respective trigger signal (one cycle high time + one cycle low time)
to the respective generator sub-block (ADC Command Generator, eT0 Trigger
Generator, eT1 Trigger Generator or Ext. Trigger Generator). This generator sub-block
then generates the requested signal. Until this real signal is generated (including guard
time) the Ready signal is kept low.
In the case of ADC command generator, the Ready signal shall be kept low until the
last conversion in the batch is finished. The respective overrun flag is set at the
following conditions:
– Ready signal is low.
– The rising edge of the respective trigger signal (from Trigger Handler to generator
sub-block) occurs.
This architecture allows the user to pre-set a trigger to the eTimer0 in the middle of an
ADC conversion, that is, the SU will be considered busy only if a request to perform the
same action that the SU is already performing occurs. One of the following bits is set:
ADC_OE, T0_OE, T1_OE, or ET_OE.
● Invalid (unrecognized) ADC command and the ICE bit is set.
● The MRS occurs before the enabled trigger events occur and the MRS_O bit is set.
● TGS overrun in sequential mode: a new incoming EV occurs before than the trigger
event selected by the previous EV occurs. The incoming EV sets an internal busy flag.
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