ST SPC560P34 - Figure 348. DMA Enable Register (DMAEN); Table 349. INTEN Field Descriptions; Table 350. DMAEN Field Descriptions

FlexPWM RM0046
662/936 Doc ID 16912 Rev 5
DMA Enable register (DMAEN)
Table 349. INTEN field descriptions
Field Description
2
REIE
Reload Error Interrupt Enable
This read/write bit enables the reload error flag (REF) to generate CPU interrupt requests. Reset
clears RIE.
0 REF CPU interrupt requests disabled.
1 REF CPU interrupt requests enabled.
3
RIE
Reload Interrupt Enable
This read/write bit enables the reload flag (RF) to generate CPU interrupt requests. Reset clears
RIE.
0 RF CPU interrupt requests disabled.
1 RF CPU interrupt requests enabled.
10:15
CMPIE
Compare Interrupt Enables
These bits enable the CMPF flags to cause a compare interrupt request to the CPU.
0 The corresponding CMPF bit will not cause an interrupt request
1 The corresponding CMPF bit will cause an interrupt request.
Figure 348. DMA Enable register (DMAEN)
Address:
Base + 0x001E (Submodule 0)
Base + 0x006E (Submodule 1)
Base + 0x00BE (Submodule 2)
Base + 0x010E (Submodule 3) Access: User read/write
0123456789101112131415
R000000
VALDE
FAND
00000000
W
Reset0000000000000000
Table 350. DMAEN field descriptions
Field Description
6
VALDE
Value Registers DMA Enable
This read/write bit enables DMA write requests for the VALx registers when RF is set. Reset clears
VALDE.
0 DMA write requests disabled.
1 DMA write requests for the VALx registers enabled.
7
FAND
FIFO Watermark AND Control
This read/write bit determines if the selected watermarks are ANDed together or ORed together in
order to create the request.
0 Selected FIFO watermarks are ORed together.
1 Selected FIFO watermarks are ANDed together.