ST SPC560P34 - Figure 145. 1-Cycle Access, no Buffering, no Prefetch

Flash Memory RM0046
324/936 Doc ID 16912 Rev 5
performance. The following diagrams illustrate operation of various cycle types and
responses referenced earlier in this chapter including stall-while-read (Figure 149) and
terminate-while-read (Figure 150) diagrams.
Figure 145. 1-cycle access, no buffering, no prefetch
nonseq
seq
seq
addr y
addr y+4 addr y+12
C(y) C(y+4)
okay okay okay okay okay okay okay okay
y
C(y) C(y+4)
Read, no buffering, no prefetch, APC = 0, RWSC = 0, PFLM = 0
123456
78
addr y
seq
addr y+8
y+4 y+8
C(y+8) C(y+12)
y+12
addr y+4 addr y+8
C(y+8)
C(y+12)
hclk
htrans
haddr, hprot
hwrite
hrdata
hwdata
hready_out
hresp
bkn_fl_addr
bkn_fl_rd_en
bkn_fl_wr_en
bkn_fl_rdata
addr+12