Deserial Serial Peripheral Interface (DSPI) RM0046
476/936 Doc ID 16912 Rev 5
Figure 226. Polarity switching between frames
20.8.6 Continuous Serial communications clock
The DSPI provides the option of generating a continuous SCK signal for slave peripherals
that require a continuous clock.
Continuous SCK is enabled by setting the CONT_SCKE bit in the DSPIx_MCR. Continuous
SCK is valid in all configurations.
Continuous SCK is only supported for CPHA = 1. Setting CPHA = 0 is ignored if the
CONT_SCKE bit is set. Continuous SCK is supported for modified transfer format.
Clock and transfer attributes for the continuous SCK mode are set according to the following
rules:
● When the DSPI is in SPI configuration, CTAR0 is used initially. At the start of each SPI
frame transfer, the CTAR specified by the CTAS for the frame is used.
● In all configurations, the currently selected CTAR remains in use until the start of a
frame with a different CTAR specified, or the continuous SCK mode is terminated.
The device is designed to use the same baud rate for all transfers made while using the
continuous SCK. Switching clock polarity between frames while using continuous SCK can
cause errors in the transfer. Continuous SCK operation is not guaranteed if the DSPI is put
into module disable mode.
Enabling continuous SCK disables the CS to SCK delay and the After SCK delay. The delay
after transfer is fixed at one SCK cycle. Figure 227 shows timing diagram for continuous
SCK format with continuous selection disabled.
Note: When in Continuous SCK mode, for the SPI transfer CTAR0 should always be used, and the
TX-FIFO must be clear using the MCR.CLR_TXF field before initiating transfer.
CS
System clock
SCK
Frame 1
Frame 0
CPOL = 0 CPOL = 1
AB
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