ST SPC560P34 - Figure 517. Once Command Register; Table 468. Once Command Register Bit Definitions

Nexus Development Interface (NDI) RM0046
896/936 Doc ID 16912 Rev 5
and/or exit functionality to be performed, even though the command appears to have no
data resource requirement associated with it.
Table 468 provides bit definitions for the Once Command Register.
R/W GO EX RS[0:6]
0123456789
Reset - 10’b1000000010 on assertion of j_trst_b or m_por, or while in the Test_Logic_Reset state
Figure 517. OnCE Command Register
Table 468. OnCE Command Register Bit Definitions
Bit(s) Name Description
0R/W
Read/Write Command Bit
The R/W bit specifies the direction of data transfer. The table below describes the options
defined by the R/W bit.
0 – Write the data associated with the command into the register specified by RS[0:6]
1 – Read the data contained in the register specified by RS[0:6]
Note: The R/W bit generally ignored for read-only or write-only registers, although the
PC FIFO pointer is only guaranteed to be update when R/W=1. In addition, it is
ignored for all bypass operations. When performing writes, most registers are
sampled in the Capture-DR state into a 32-bit shift register, and subsequently shifted
out on j_tdo during the first 32 clocks of Shift-DR.
1GO
Go Command Bit
0 – Inactive (no action taken)
1 – Execute instruction in IR
If the GO bit is set, the chip will execute the instruction which resides in the IR register in the
CPUSCR. To execute the instruction, the processor leaves the debug mode, executes the
instruction, and if the EX bit is cleared, returns to the debug mode immediately after
executing the instruction. The processor goes on to normal operation if the EX bit is set, and
no other debug request source is asserted. The GO command is executed only if the
operation is a read/write to CPUSCR or a read/write to “No Register Selected”. Otherwise
the GO bit is ignored.The processor will leave the debug mode after the TAP controller
Update-DR state is entered.
On a GO+NoExit operation, returning to debug mode is treated as a debug event, thus
exceptions such as machine checks and interrupts may take priority and prevent execution
of the intended instruction. Debug firmware should mask these exceptions as appropriate.
The OSR
ERR
bit indicates such an occurrence.
Note that asynchronous interrupts are blocked on a GO+Exit operation until the first
instruction to be executed begins execution.