ST SPC560P34 - System Clock Divider Configuration Register (CGM_SC_DC0); Table 28. System Clock Select Status Register (CGM_SC_SS) Field Descriptions; Table 29. System Clock Divider Configuration Register (CGM_SC_DC0) Field Descriptions; Figure 30. System Clock Divider Configuration Register (CGM_SC_DC0)

Clock Generation Module (MC_CGM) RM0046
126/936 Doc ID 16912 Rev 5
5.5.4 System Clock Divider Configuration Register (CGM_SC_DC0)
This register controls the system clock divider.
Table 28. System Clock Select Status Register (CGM_SC_SS) Field Descriptions
Field Description
SELSTAT
System Clock Source Selection Status — This value indicates the current source for the system
clock.
0000 16 MHz int. RC osc.
0001 reserved
0010 4 MHz crystal osc.
0011 reserved
0100 system PLL
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled
Figure 30. System Clock Divider Configuration Register (CGM_SC_DC0)
Address 0xC3FE_037C Access: User read, Supervisor read/write, Test read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0123456789101112131415
R
DE0
000
DIV0
00000000
W
Reset1000000000000000
1514131211109876543210
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W
Reset0000000000000000
Table 29. System Clock Divider Configuration Register (CGM_SC_DC0) Field Descriptions
Field Description
DE0
Divider 0 Enable
0 Disable system clock divider 0
1 Enable system clock divider 0
DIV0
Divider 0 Division Value — The resultant divided system clock 0 will have a period DIV0 + 1 times that
of the system clock. If the DE0 is set to ‘0’ (Divider 0 is disabled), any write access to the DIV0 field is
ignored and the divided system clock 0 remains disabled.