Introduction RM0046
54/936 Doc ID 16912 Rev 5
● Branch processing acceleration using lookahead instruction buffer
● Load/store unit
– 1-cycle load latency
– Misaligned access support
– No load-to-use pipeline bubbles
● Thirty-two 32-bit general purpose registers (GPRs)
● Separate instruction bus and load/store bus Harvard architecture
● Hardware vectored interrupt support
● Reservation instructions for implementing read-modify-write constructs
● Long cycle time instructions, except for guarded loads, do not increase interrupt latency
● Extensive system development support through Nexus debug port
● Non-maskable interrupt support
1.6.2 Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between three
master ports and three slave ports. The crossbar supports a 32-bit address bus width and a
32-bit data bus width.
The crossbar allows for two concurrent transactions to occur from any master port to any
slave port; but one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic will select the higher priority master and grant it ownership of the slave port.
All other masters requesting that slave port will be stalled until the higher priority master
completes its transactions. Requesting masters will be treated with equal priority and will be
granted access a slave port in round-robin fashion, based upon the ID of the last master to
be granted access.
The crossbar provides the following features:
● 3 master ports:
– e200z0 core complex instruction port
– e200z0 core complex Load/Store Data port
–eDMA
● 3 slave ports:
– Flash memory (Code and Data)
–SRAM
– Peripheral bridge
● 32-bit internal address, 32-bit internal data paths
● Fixed Priority Arbitration based on Port Master
● Temporary dynamic priority elevation of masters
1.6.3 Enhanced direct memory access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual
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