ST SPC560P34 - Analog Clock Generator and Conversion Timings

Analog-to-Digital Converter (ADC) RM0046
580/936 Doc ID 16912 Rev 5
Abort conversion
Two different abort functions are provided.
● The user can abort the ongoing conversion by setting the MCR[ABORT] bit. The
current conversion is aborted and the conversion of the next channel of the chain is
immediately started. In the case of an abort operation, the NSTART/JSTART bit
remains set and the ABORT bit is reset after the conversion of the next channel starts.
The EOC interrupt corresponding to the aborted channel is not generated. This
behavior is true for normal or triggered/Injected conversion modes. If the last channel of
a chain is aborted, the end of chain is reported generating an ECH interrupt.
● It is also possible to abort the current chain conversion by setting the
MCR[ABORTCHAIN] bit. In that case the behavior of the ADC depends on the MODE
bit. If scan mode is disabled, the NSTART bit is automatically reset together with the
MCR[ABORTCHAIN] bit. Otherwise, if the scan mode is enabled, a new chain
conversion is started. The EOC interrupt of the current aborted conversion is not
generated but an ECH interrupt is generated to signal the end of the chain.
When a chain conversion abort is requested (ABORTCHAIN bit is set) while an injected
conversion is running over a suspended Normal conversion, both injected chain and
Normal conversion chain are aborted (both the NSTART and JSTART bits are also
reset).
23.3.2 Analog clock generator and conversion timings
The clock frequency can be selected by programming the MCR[ADCLKSEL]. When this bit
is set to ‘1’ the ADC clock has the same frequency as the MC_PLL_CLK. Otherwise, the
ADC clock is half of the MC_PLL_CLK frequency. The ADCLKSEL bit can be written only in
power-down mode.
When the internal divider is not enabled (ADCCLKSEL = 1), it is important that the
associated clock divider in the clock generation module is ‘1’. This is needed to ensure 50%
clock duty cycle.
The direct clock should basically be used only in low power mode when the device is using
only the 16 MHz fast internal RC oscillator, but the conversion still requires a 16 MHz clock
(an 8 MHz clock is not fast enough).
In all other cases, the ADC should use the clock divided by two internally.
Depending on the position of the rising edge of the signal internal trigger signal coming from
the CTU, the ADC clock could also be stretched as illustrated in Figure 282.