IEEE 1149.1 Test Access Port Controller (JTAGC) RM0046
846/936 Doc ID 16912 Rev 5
35.8.3 TAP controller state machine
The TAP controller is a synchronous state machine that interprets the sequence of logical
values on the TMS pin. Figure 501 shows the machine’s states. The value shown next to
each state is the value of the TMS signal sampled on the rising edge of the TCK signal.
As Figure 501 shows, holding TMS at logic 1 while clocking TCK through a sufficient
number of rising edges also causes the state machine to enter the test-logic-reset state.
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