FlexCAN RM0046
540/936 Doc ID 16912 Rev 5
22.3.3 Rx FIFO structure
When the FEN bit is set in the MCR, the memory area from 0x80 to 0xFF (which is normally
occupied by MBs 0 to 7) is used by the reception FIFO engine. Figure 264 shows the Rx
FIFO data structure. The region 0x00–0x0C contains an MB structure that is the port
through which the CPU reads data from the FIFO (the oldest frame received and not read
yet). The region 0x10–0xDF is reserved for internal use of the FIFO engine. The region
0xE0–0xFF contains an 8-entry ID table that specifies filtering criteria for accepting frames
into the FIFO. Table 2 7 1 shows the three different formats that the elements of the ID table
can assume, depending on the IDAM field of the MCR. Note that all elements of the table
must have the same format. See Section 22.4.7, “Rx FIFO for more information.
Base + 0x00D0 MB5 Base + 0x01D0 MB21
Base + 0x00E0 MB6 Base + 0x01E0 MB22
Base + 0x00F0 MB7 Base + 0x01F0 MB23
Base + 0x0100 MB8 Base + 0x0200 MB24
Base + 0x0110 MB9 Base + 0x0210 MB25
Base + 0x0120 MB10 Base + 0x0220 MB26
Base + 0x0130 MB11 Base + 0x0230 MB27
Base + 0x0140 MB12 Base + 0x0240 MB28
Base + 0x0150 MB13 Base + 0x0250 MB29
Base + 0x0160 MB14 Base + 0x0260 MB30
Base + 0x0170 MB15 Base + 0x0270 MB31
Table 270. MB0–MB31 addresses (continued)
Address Register Address Register
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