Deserial Serial Peripheral Interface (DSPI) RM0046
460/936 Doc ID 16912 Rev 5
DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn)
The DSPIx_RXFRn registers provide visibility into the RX FIFO for debugging purposes.
Each register is an entry in the RX FIFO. The DSPIx_RXFR registers are read-only.
Reading the DSPIx_RXFRn registers does not alter the state of the RX FIFO. The device
uses five registers to implement the RX FIFO, that is DSPIx_RXFR0–DSPIx_RXFR4 are
used.
20.8 Functional description
The DSPI supports full-duplex, synchronous serial communications between the MCU and
peripheral devices. All communications are through an SPI-like protocol.
The DSPI supports only the serial peripheral interface (SPI) configuration in which the DSPI
operates as a basic SPI or a queued SPI.
Table 219. DSPIx_TXFRn field descriptions
Field Description
0–15
TXCMD
[0:15]
Transmit command
Contains the command that sets the transfer attributes for the SPI data. Refer to Section ,
“DSPI PUSH TX FIFO Register (DSPIx_PUSHR) for details on the command field.
16–31
TXDATA
[0:15]
Transmit data
Contains the SPI data to be shifted out.
Figure 215. DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn)
Address:
Base + 0x007C (DSPIx_RXFR0)
Base + 0x0080 (DSPIx_RXFR1)
Base + 0x0084 (DSPIx_RXFR2)
Base + 0x0088 (DSPIx_RXFR3)
Base + 0x008C
(DSPIx_RXFR4)
Access: User read-only
0123456789101112131415
R00000000 00000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RRXDATA
W
Reset0000000000000000
Table 220. DSPIx_RXFRn field description
Field Description
0–15 Reserved, must be cleared.
16–31
RXDATA
[15:0]
Receive data
Contains the received SPI data.