ST SPC560P34 - Table 184. EDMA_CIRQR Field Descriptions; Table 185. EDMA_CERR Field Descriptions; Figure 185. Edma Clear Interrupt Request (EDMA_CIRQR); Figure 186. Edma Clear Error Register (EDMA_CERR)

Enhanced Direct Memory Access (eDMA) RM0046
394/936 Doc ID 16912 Rev 5
eDMA Clear Error Register (EDMA_CERR)
The EDMA_CERR provides a simple memory-mapped mechanism to clear a given bit in the
EDMA_ERL to disable the error condition flag for a given channel. The given value on a
register write causes the corresponding bit in the EDMA_ERL to be cleared. Setting bit 1
(CERn) provides a global clear function, forcing the entire contents of the EDMA_ERL to be
zeroed, clearing all channel error indicators. Reads of this register return all zeroes.
Figure 185. eDMA Clear Interrupt Request (EDMA_CIRQR)
Address: Base + 0x001C Access: User write-only
01234567
R00000000
W
CINT[0:6]
Reset00000000
Table 184. EDMA_CIRQR field descriptions
Field Description
0 Reserved.
1–7
CINT[0:6]
Clear interrupt request.
0–15 Clear corresponding bit in EDMA_IRQRL
16–63 Reserved
64–127 Clear all bits in EDMA_IRQRL
Bit 2 (CINT1) is not used.
Figure 186. eDMA Clear Error Register (EDMA_CERR)
Address: Base + 0x001D Access: User write-only
01234567
R00000000
W
CERR[0:6]
Reset00000000
Table 185. EDMA_CERR field descriptions
Field Description
0 Reserved.
1–7
CER[0:6]
Clear error indicator.
0–15 Clear corresponding bit in EDMA_ERL
16–63 Reserved
64–127 Clear all bits in EDMA_ERL