ST SPC560P34 - Table 71. INTC_IACKR Field Descriptions; Figure 80. INTC Interrupt Acknowledge Register (INTC_IACKR)

RM0046 Interrupt Controller (INTC)
Doc ID 16912 Rev 5 215/936
INTC Interrupt Acknowledge Register(INTC_IACKR)
The interrupt acknowledge register provides a value that can be used to load the address of
an ISR from a vector table. The vector table can be composed of addresses of the ISRs
specific to their respective interrupt vectors.
In software vector mode, the INTC_IACKR has side effects from reads. Therefore, it must
not be speculatively read while in this mode. The side effects are the same regardless of the
size of the read. Reading the INTC_IACKR does not have side effects in hardware vector
mode.
Figure 80. INTC Interrupt Acknowledge Register (INTC_IACKR)
Address Base + 0x0010 Access: User read/write
0123456789101112131415
R
VTBA (most significant 16 bits)
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
VTBA
(least significant 5 bits)
INTVEC
1
0 0
W
Reset0000000000000000
1. When the VTES bit in INTC_MCR is asserted, INTVEC is shifted to the left one bit. Bit 29 is read as a ‘0’. VTBA
is narrowed to 20 bits in width.
Table 71. INTC_IACKR field descriptions
Field Description
0–20
or
0–19
VTBA
Vector Table Base Address
Can be the base address of a vector table of addresses of ISRs. The VTBA only uses the
leftmost 20 bits when the VTES bit in INTC_MCR is asserted.
21–29
or
20–28
INTVEC
Interrupt Vector
It is the vector of the peripheral or software configurable interrupt request that caused the
interrupt request to the processor. When the interrupt request to the processor asserts, the
INTVEC is updated, whether the INTC is in software or hardware vector mode.
Note: If INTC_MCR[VTES] = 1, then the INTVEC field is shifted left one position to bits 20–28.
VTBA is then shortened by one bit to bits 0–19.