ST SPC560P34 - Figure 400. Control Register 2 (CTRL2); Table 374. CTRL2 Field Descriptions

eTimer RM0046
716/936 Doc ID 16912 Rev 5
Control register 2 (CTRL2)
01100 Reserved 11100 IP Bus clock divide by 16 prescaler
01101 Reserved 11101 IP Bus clock divide by 32 prescaler
01110 Reserved 11110 IP Bus clock divide by 64 prescaler
01111 Reserved 11111 IP Bus clock divide by 128 prescaler
Table 373. Count source values (continued)
Value Meaning Value Meaning
Figure 400. Control register 2 (CTRL2)
Address:
Base + 0x0010 (eTimer0)
Base + 0x0030 (eTimer1)
Base + 0x0050 (eTimer2)
Base + 0x0070 (eTimer3)
Base + 0x0090 (eTimer4)
Base + 0x00B0 (eTimer5)
Access: User read/write
0123456789101112131415
R
OEN RDNT
INPUT
VAL
0
COFRC
COINIT SIPS PIPS OPS MSTR OUTMODE[3:0]
W
FORCE
Reset0000000000000000
Table 374. CTRL2 field descriptions
Field Description
OEN
Output Enable
This bit determines the direction of the external pin.
0 The external pin is configured as an input.
1 OFLAG output signal is driven on the external pin. Other timer channels using this external pin
as their input will see the driven value. The polarity of the signal will be determined by the OPS bit.
RDNT
Redundant Channel Enable
This bit enables redundant channel checking between adjacent channels (0 and 1, 2 and 3, 4 and
5). When this bit is cleared, the RCF bit in this channel cannot be set. When this bit is set, the RCF
bit is set by a miscompare between the OFLAG of this channel and the OFLAG of its redundant
adjacent channel, which causes the output of this channel to go inactive (logic 0 prior to
consideration of the OPS bit).
0Disable redundant channel checking.
1Enable redundant channel checking.
INPUT
External input signal
This read only bit reflects the current state of the signal selected via SECSRC after application of
the SIPS bit and filtering.
VAL
Forced OFLAG Value
This bit determines the value of the OFLAG output signal when a software triggered FORCE
command occurs.