ST SPC560P34 - Functional Description; General; Pad Control; General Purpose Input and Output Pads (GPIO)

RM0046 System Integration Unit Lite (SIUL)
Doc ID 16912 Rev 5 267/936
11.6 Functional description
11.6.1 General
This section provides a functional description of the System Integration Unit Lite.
11.6.2 Pad control
The SIUL controls the configuration and electrical characteristic of the device pads. It
provides a consistent interface for all pads, both on a by-port and a by-bit basis. The SIUL
allows each pad to be configured as either a General Purpose Input Output pad (GPIO), and
as one or more alternate functions (input or output). The pad configuration registers (PCRn,
see Section , “Pad Configuration Registers (PCR[0:71])) allow software control of the static
electrical characteristics of external pins with a single write. These configure the following
pad features:
● Open drain output enable
● Slew rate control
● Pull control
● Pad assignment
● Control of analog path switches
● Safe mode behavior configuration
11.6.3 General purpose input and output pads (GPIO)
The SIUL allows each pad to be configured as either a General Purpose Input Output pad
(GPIO), and as one or more alternate functions (input or output), the function of which is
normally determined by the peripheral that uses the pad.
The SIUL manages up to 64 GPIO pads organized as ports that can be accessed for data
reads and writes as 32-bit, 16-bit or 8-bit.
As shown in Figure 114, all port accesses are identical with each read or write being
performed only at a different location to access a different port width.
Figure 114. Data port example arrangement showing configuration for different port
width accesses
This implementation requires that the registers are arranged in such a way as to support this
range of port widths without having to split reads or writes into multiple accesses.
The SIUL has separate data input (GPDIn_n, see Section , “GPIO Pad Data Input registers
0_3–68_71 (GPDI[0_3:68_71])) and data output (GPDOn_n, see Section , “GPIO Pad Data
Output registers 0_3–68_71 (GPDO[0_3:68_71])) registers for all pads, allowing the
31
23 15 7 0
SIUL Base +
15 7 0
SIUL Base +
15 7 0
SIUL Base +
70
0x0003
SIUL Base +
70
0x0002
SIUL Base +
70
0x0001
SIUL Base +
70
0x0000
0x0002
0x0000
32-bit Port
16-bit Port
16-bit Port
8-bit Port
8-bit Port
8-bit Port
8-bit Port
SIUL Base + 0x0000