ST SPC560P34 - Table 186. EDMA_SSBR Field Descriptions; Figure 187. Edma Set START Bit Register (EDMA_SSBR); Figure 188. Edma Clear DONE Status Bit Register (EDMA_CDSBR)

RM0046 Enhanced Direct Memory Access (eDMA)
Doc ID 16912 Rev 5 395/936
eDMA Set START Bit Register (EDMA_SSBR)
The EDMA_SSBR provides a simple memory-mapped mechanism to set the START bit in
the TCD of the given channel. The data value on a register write causes the START bit in the
corresponding transfer control descriptor to be set. Setting bit 1 (SSBn) provides a global
set function, forcing all START bits to be set. Reads of this register return all zeroes.
eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
The EDMA_CDSBR provides a simple memory-mapped mechanism to clear the DONE bit
in the TCD of the given channel. The data value on a register write causes the DONE bit in
the corresponding transfer control descriptor to be cleared. Setting bit 1 (CDSBn) provides a
global clear function, forcing all DONE bits to be cleared.
Figure 187. eDMA Set START Bit Register (EDMA_SSBR)
Address: Base + 0x001E Access: User write-only
01234567
R00000000
W
SSB[0:6]
Reset00000000
Table 186. EDMA_SSBR field descriptions
Field Description
0 Reserved.
1–7
SSB[0:6]
Set START bit (channel service request).
0–15 Set the corresponding channel’s TCD START bit
16–63 Reserved
64–127 Set all TCD START bits
Bit 2 (SSB1) is not used.
Figure 188. eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
Address: Base + 0x001F Access: User write-only
01234567
R00000000
W
CDSB[0:6]
Reset00000000