Functional Safety RM0046
746/936 Doc ID 16912 Rev 5
The SWT provides a window functionality. When this functionality is programmed, the
servicing action should take place within the defined window. When occurring outside the
defined period, the SWT will generate a reset.
27.3.2 Features
The SWT has the following features:
● 32-bit time-out register to set the time-out period
● The unique SWT counter clock is the undivided low power internal oscillator (IRC
16 MHz), no other clock source can be selected
● Programmable selection of window mode or regular servicing
● Programmable selection of reset or interrupt on an initial time-out
● Master access protection
● Hard and soft configuration lock bits
● The SWT is started on exit of power-on phase (RGM phase 2) to monitor flash boot
sequence phase. It is then reset during RGM phase 3 and optionally enabled when
platform reset is released depending on value of flash user option bit 31
(WATCHDOG_EN).
27.3.3 Modes of operation
The SWT supports three device modes of operation: normal, debug and stop. When the
SWT is enabled in normal mode, its counter runs continuously. In debug mode, operation of
the counter is controlled by the FRZ bit in the SWT_CR. If the FRZ bit is set, the counter is
stopped in debug mode, otherwise it continues to run. In stop mode, operation of the
counter is controlled by the STP bit in the SWT_CR. If the STP bit is set, the counter is
stopped in stop mode, otherwise it continues to run. As soon as out of stop mode, SWT will
continue from the state it was before entering this mode.
Software watchdog is not available during stand-by. As soon as out of stand-by, the SWT
behaves as in a usual “out of reset” situation.
27.3.4 External signal description
The SWT module does not have any external interface signals.
27.3.5 SWT memory map and registers description
The SWT programming model has six 32-bit registers, listed in Ta ble 391 . The programming
model can only be accessed using 32-bit (word) accesses. References using a different size
are invalid. Other types of invalid accesses include: writes to read only registers, incorrect
values written to the service register when enabled, accesses to reserved addresses and
accesses by masters without permission. If the RIA bit in the SWT_CR is set, the SWT
generates a system reset on an invalid access. Otherwise, a bus error is generated. If either
the HLK or SLK bits in the SWT_CR are set, then the SWT_CR, SWT_TO and SWT_WN
registers are read only.
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