Crossbar Switch (XBAR) RM0046
282/936 Doc ID 16912 Rev 5
14.3 Overview
The XBAR allows for concurrent transactions to occur from any master port to any slave
port. It is possible for all master ports and slave ports to be in use at the same time as a
result of independent master requests. If a slave port is simultaneously requested by more
than one master port, arbitration logic selects the higher priority master and grants it
ownership of the slave port. All other masters requesting that slave port are stalled until the
higher priority master completes its transactions.
Requesting masters are granted access based on a fixed priority.
14.4 Features
● 3 Master ports
– e200z0 core complex Instruction port
– e200z0 core complex Load/Store Data port
–eDMA
● 3 Slave ports
– Flash memory (code and data)
– Internal SRAM
– Peripheral bridge
● 32-bit internal address, 32-bit internal data paths
● Fully concurrent transfers between independent master and slave ports
● Fixed priority scheme and fixed parking strategy
14.5 Modes of operation
14.5.1 Normal mode
In normal mode, the XBAR provides the register interface and logic that controls crossbar
switch configuration.
14.5.2 Debug mode
The XBAR operation in debug mode is identical to operation in normal mode.
14.6 Functional description
This section describes the functionality of the XBAR in more detail.
14.6.1 Overview
The main goal of the XBAR is to increase overall system performance by allowing multiple
masters to communicate concurrently with multiple slaves. To maximize data throughput, it
is essential to keep arbitration delays to a minimum.
This section examines data throughput from the point of view of masters and slaves,
detailing when the XBAR stalls masters, or inserts bubbles on the slave side.
To Next Page
Loading...
