ST SPC560P34 - External Signal Description; Memory Map and Register Definition; Table 56. MC_RGM Register Description

Reset Generation Module (MC_RGM) RM0046
190/936 Doc ID 16912 Rev 5
phase completion gates from either the system or internal to the MC_RGM are
acknowledged. The device reset associated with the phase is then released, and the state
machine proceeds to the next phase up to entering the IDLE phase. During this entire
process, the MC_ME state machine is held in RESET mode. Only at the end of the reset
sequence, when the IDLE phase is reached, does the MC_ME enter the DRUN mode.
Alternatively, it is possible for software to configure some reset source events to be
converted from a reset to either a SAFE mode request issued to the MC_ME or to an
interrupt issued to the core (see Section , “Functional Event Reset Disable Register
(RGM_FERD) and Section , “Functional Event Alternate Request Register (RGM_FEAR) for
‘functional’ resets).
8.2 External Signal Description
The MC_RGM interfaces to the bidirectional reset pin RESET_B and the boot mode pins
PAD[4:2].
8.3 Memory Map and Register Definition
Note: Any access to unused registers as well as write accesses to read-only registers will not
change register content, and cause a transfer error.
Table 56. MC_RGM Register Description
Address Name Description Size
Access
Location
User Supervisor Test
0xC3FE
_4000
RGM_FES Functional Event Status half-word read read/write
(1)
read/write
(1)
on page 8-
192
0xC3FE
_4002
RGM_DES Destructive Event Status half-word read read/write
(1)
read/write
(1)
on page 8-
194
0xC3FE
_4004
RGM_FERD
Functional Event Reset
Disable
half-word read read/write
(2)
read/write
(2)
on page 8-
195
0xC3FE
_4006
RGM_DERD
Destructive Event Reset
Disable
half-word read read read
on page 8-
197
0xC3FE
_4010
RGM_FEAR
Functional Event Alternate
Request
half-word read read/write read/write
on page 8-
198
0xC3FE
_4018
RGM_FESS
Functional Event Short
Sequence
half-word read read/write read/write
on page 8-
199
0xC3FE
_401C
RGM_FBRE
Functional Bidirectional
Reset Enable
half-word read read/write read/write
on page 8-
200
1. individual bits cleared on writing ‘1’
2. write once: ‘0’ = enable, ‘1’ = disable.