RM0046 eTimer
Doc ID 16912 Rev 5 735/936
The arming logic controls the operation of the capture circuits to allow captures to be
performed in a free-running (continuous) or one-shot fashion. In free-running mode, the
capture sequences will be performed indefinitely. If both capture circuits are enabled, they
will work together in a ping-pong style where a capture event from one circuit leads to the
arming of the other and vice versa. In one-shot mode, only one capture sequence will be
performed. If both capture circuits are enabled, capture circuit 0 is armed first. When a
capture event occurs, capture circuit 1 is armed. Once the second capture occurs, further
captures are disabled until another capture sequence is initiated. Both capture circuits are
capable of generating an interrupt to the CPU.
Master/Slave mode
Any timer channel can be assigned as a Master (MSTR = 1). A Master’s compare signal can
be broadcast to the other channels within the module. The other counters can be configured
to reinitialize their counters (COINIT = 1) and/or force their OFLAG output signals
(COFRC = 1) to predetermined values when a Master counter compare event occurs.
Watchdog timer
The watchdog timer monitors for a stalled count when channel 0 is in quadrature count
mode. When the watchdog is enabled, it loads the time-out value into a down counter. The
down counter counts as long as channel 0 is in quadrature decode count mode. If this down
counter reaches 0, an interrupt is asserted. The down counter is reloaded to the time-out
value each time the counter value from channel 0 changes. If the channel 0 count value is
toggling between two values (indicating a possibly stalled encoder), then the down counter
is not reloaded.
26.8 Clocks
The eTimer module implements a protocol clock running at a frequency 120 MHz.
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