ST SPC560P34 - Figure 49. Debug Mode Transition Status Register (ME

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RM0046 Mode Entry Module (MC_ME)

Doc ID 16912 Rev 5 155/936

Debug Mode Transition Status Register (ME_DMTS)

This register provides the status of different factors which influence mode transitions. It is

used to give an indication of why a mode transition indicated by ME_GS.S_MTRANS may

be taking longer than expected.

Note: The ME_DMTS register does not indicate whether a mode transition is ongoing. Therefore,

some ME_DMTS bits may still be asserted after the mode transition has completed.

Figure 49. Debug Mode Transition Status Register (ME_DMTS)

Address 0xC3FD_C018 Access: User read, Supervisor read/write, Test read/write

0123456789101112131415

R PREVIOUS_MODE 0 0 0 0

MPH_BUSY

PMC_PROG

CORE_DBG

SMR

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

VREG_CSRC_SC

CSRC_CSRC_SC

16 MHz_IRC_SC

SCSRC_SC

SYSCLK_SW

DFLASH_SC

CFLASH_SC

CDP_PRPH_0_143

0000

CDP_PRPH_64_95

CDP_PRPH_32_63

CDP_PRPH_0_31

Reset0000000000000000

ST SPC560P34 - Figure 49. Debug Mode Transition Status Register (ME_DMTS)