Interrupt Controller (INTC) RM0046
212/936 Doc ID 16912 Rev 5
9.5 Memory map and registers description
9.5.1 Module memory map
Table 6 8 shows the INTC memory map.
9.5.2 Registers description
With exception of the INTC_SSCIn and INTC_PSRn, all registers are 32 bits in width. Any
combination of accessing the four bytes of a register with a single access is supported,
provided that the access does not cross a register boundary. These supported accesses
include types and sizes of 8 bits, aligned 16 bits, misaligned 16 bits to the middle 2 bytes,
and aligned 32 bits.
Although INTC_SSCIn and INTC_PSRn are 8 bits wide, they can be accessed with a single
16-bit or 32-bit access, provided that the access does not cross a 32-bit boundary.
In software vector mode, the side effects of a read of INTC_IACKR are the same regardless
of the size of the read. In either software or hardware vector mode, the size of a write to
either INTC_SSCIR0_3–INTC_SSCIR4_7 or INTC_EOIR does not affect the operation of
the write.
INTC registers are accessible only when the core is in supervisor mode (see Section 15.4.3,
“ECSM_reg_protection).
Table 68. INTC memory map
Offset from
INTC_BASE
0xFFF4_8000
Register Location
0x0000 INTC Module Configuration Register (INTC_MCR) on page 9-213
0x0004 Reserved
0x0008 INTC Current Priority Register (INTC_CPR) on page 9-213
0x000C Reserved
0x0010 INTC Interrupt Acknowledge Register(INTC_IACKR) on page 9-215
0x0014 Reserved
0x0018 INTC End-of-Interrupt Register (INTC_EOIR) on page 9-216
0x001C Reserved
0x0020–0x0027
INTC Software Set/Clear Interrupt Registers
(INTC_SSCIR0_3–INTC_SSCIR4_7)
on page 9-216
0x0028– 0x003C Reserved
0x0040–0x011C
INTC Priority Select Registers (INTC_PSR0_3–
INTC_PSR220_221)
(1)
1. The PRI fields are “reserved” for peripheral interrupt requests whose vectors are labeled as Reserved in
Table 75.
on page 9-218
0x0120–0x3FFF
Reserved
To Next Page
Loading...
