RM0046 Analog-to-Digital Converter (ADC)
Doc ID 16912 Rev 5 575/936
23 Analog-to-Digital Converter (ADC)
23.1 Overview
23.1.1 Device-specific features
● 1 ADC unit
● 10-bit resolution
● 16 input channels
– 15 channels on 100-pin LQFP; 11 channels on 64-pin LQFP
– Channel 15 dedicated to the internal 1.2 V rail
● Conversion time < 1 µs including sampling time at full precision (conversion time target
of 700 ns for the analog section)
● Cross triggering unit (CTU)
● 4 analog watchdogs with interrupt capability for continuous hardware monitoring of as
many as 4 analog input channels
● Clock stretching (with CTU pulse)
● Sampling and conversion time register CTR0 (internal precision channels)
● Left-aligned result format
● Right-aligned result format
● One Shot/Scan Modes
● Chain Injection Mode
● Power-down mode
● 2 different Abort functions allow aborting either single-channel conversion or chain
conversion
● As many as 16 data registers for storing converted data. Conversion information, such
as mode of operation (normal, injected or CTU), is associated to data value.
● Auto-clock-off
● 2 modes of operation, each with DMA compatible interface
– Normal Mode
– CTU Control Mode
These features are absent on the device:
● Support of external channels
● Presampling
● Alternate analog thresholds
● Offset Cancellation and Offset Refresh Control
● External start and triggering
23.1.2 Device-specific pin configuration features
● For Section 23.3.3, ADC sampling and conversion timing,” f
ck
= (1/2) MC_PLL_CLK is
true where the bit ADCLKSEL would be always 0 (default value), meaning that AD_clk
is half of MC_PLL_CLK. A clock prescaler (1 or 2) can be configured. The AD_clk has
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