Deserial Serial Peripheral Interface (DSPI) RM0046
462/936 Doc ID 16912 Rev 5
Master mode
In master mode the DSPI can initiate communications with peripheral devices. The DSPI
operates as bus master when the MSTR bit in the DSPIx_MCR is set. The serial
communications clock (SCK) is controlled by the master DSPI. All three DSPI configurations
are valid in master mode.
In SPI configuration, master mode transfer attributes are controlled by the SPI command in
the current TX FIFO entry. The CTAS field in the SPI command selects which of the eight
DSPIx_CTARs set the transfer attributes. Transfer attribute control is on a frame by frame
basis.
Refer to Section 20.8.3, “Serial Peripheral Interface (SPI) configuration for more details.
Slave mode
In slave mode the DSPI responds to transfers initiated by an SPI master. The DSPI operates
as bus slave when the MSTR bit in the DSPIx_MCR is negated. The DSPI slave is selected
by a bus master by having the slave’s CS0_
x asserted. In slave mode, the SCK is provided
by the bus master. All transfer attributes are controlled by the bus master, except the clock
polarity, clock phase, and the number of bits to transfer. These must be configured in the
DSPI slave for correct communications.
Module disable mode
The module disable mode is used for MCU power management. The clock to the non-
memory mapped logic in the DSPI is stopped while in module disable mode. The DSPI
enters the module disable mode when the MDIS bit in DSPIx_MCR is set.
Refer to Section 20.8.8, “Power saving features for more details on the module disable
mode.
Debug mode
The debug mode is used for system development and debugging. If the MCU enters debug
mode while the FRZ bit in the DSPIx_MCR is set, the DSPI stops all serial transfers and
enters a stopped state. If the MCU enters debug mode while the FRZ bit is cleared, the
DSPI behavior is unaffected and remains dictated by the module-specific mode and
configuration of the DSPI. The DSPI enters debug mode when a debug request is asserted
by an external controller.
Refer to Figure 217 for a state diagram.
20.8.2 Start and stop of DSPI transfers
The DSPI has two operating states: STOPPED and RUNNING. The states are independent
of DSPI configuration. The default state of the DSPI is STOPPED. In the STOPPED state no
serial transfers are initiated in master mode and no transfers are responded to in slave
mode. The STOPPED state is also a safe state for writing the various configuration registers
of the DSPI without causing undetermined results. The TXRXS bit in the DSPIx_SR is
cleared in this state. In the RUNNING state, serial transfers take place. The TXRXS bit in the
DSPIx_SR is set in the RUNNING state.
Figure 217 shows a state diagram of the start and stop mechanism.
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