ST SPC560P34 - Table 293. Example for Analog Watchdog Operation; DMA Functionality

RM0046 Analog-to-Digital Converter (ADC)
Doc ID 16912 Rev 5 585/936
WDGxH for high threshold violation is set. Thus, the user should avoid that situation as it
could lead to misinterpretation of the watchdog interrupts.
Analog watchdog functionality
For each input channel the result of the comparison is reflected in the THROP bit in TRC
register based on the converted analog values received by the analog watchdogs:
● If the converted data value is lower than the lower threshold then the THROP bit in TRC
register will be set to 1.
● If the converted voltage is higher than the higher threshold then the THROP bit in TRC
register will be set to 0.
● If the converted voltage lies between the upper and the lower threshold guard window
then THROP bit in TRC register will keep its logic value.
The logic level of the THROP bit can be programmed by software. In fact, the user can
decide to keep the behavior described or to invert the output logic level by setting the
THRINV bit in the TRC register.
An example of the operation is shown in Ta bl e 2 93.
23.3.6 DMA functionality
A DMA request can be programmed after the conversion of every channel by setting the
respective masking bit in the DMAR registers. The DMAR masking registers must be
programmed before starting any conversion. There is one DMAR per channel type.
The DMA transfers can be enabled using the DMAEN bit of DMAE register. When the DCLR
bit of DMAE register is set, the DMA request is cleared the register enabled for DMA transfer
has been read.
23.3.7 Interrupts
The ADC generates the following maskable interrupt signals:
● EOC (end of conversion) interrupt request
● ECH (end of chain) interrupt request
● JEOC (end of injected conversion) interrupt request
● JECH (end of injected chain) interrupt request
● EOCTU (end of CTU conversion) interrupt request
● WDGxL and WDGxH (watchdog threshold) interrupt requests
Interrupts are generated during the conversion process to signal events such as End Of
Conversion as explained in register description for ISR and IMR.
Table 293. Example for Analog watchdog operation
Converted data
watchdog[x]
Upper threshold
watchdog[x]
Lower threshold
watchdog[x]
THRINV
watchdog[x]
THROP[x]
155h 055h 000h 0 0
055h 1ffh 088h 0 1
155h 055h 000h 1 1
055h 1ffh 088h 1 0