ST SPC560P34 - Table 233. Linflex Memory Map; Figure 234. Linflex in Self Test Mode; Memory Map and Registers Description

RM0046 LIN Controller (LINFlex)
Doc ID 16912 Rev 5 491/936
Figure 234. LINFlex in self test mode
21.7 Memory map and registers description
21.7.1 Memory map
See the “Memory map” chapter of this reference manual for the base addresses for the
LINFlex modules.
Table 233 shows the LINFlex memory map.
LINFlex
LINTX LINRX
Tx Rx
=1
Table 233. LINFlex memory map
Address offset Register Location
0x0000 LIN control register 1 (LINCR1) on page 21-492
0x0004 LIN interrupt enable register (LINIER) on page 21-495
0x0008 LIN status register (LINSR) on page 21-497
0x000C LIN error status register (LINESR) on page 21-500
0x0010 UART mode control register (UARTCR) on page 21-501
0x0014 UART mode status register (UARTSR) on page 21-503
0x0018 LIN timeout control status register (LINTCSR) on page 21-505
0x001C LIN output compare register (LINOCR) on page 21-506
0x0020 LIN timeout control register (LINTOCR) on page 21-506
0x0024 LIN fractional baud rate register (LINFBRR) on page 21-507
0x0028 LIN integer baud rate register (LINIBRR) on page 21-508
0x002C LIN checksum field register (LINCFR) on page 21-509
0x0030 LIN control register 2 (LINCR2) on page 21-509
0x0034 Buffer identifier register (BIDR) on page 21-511
0x0038 Buffer data register LSB (BDRL)
(1)
on page 21-512
0x003C Buffer data register MSB (BDRM)
(2)
on page 21-512
0x0040 Identifier filter enable register (IFER) on page 21-513