Periodic Interrupt Timer (PIT) RM0046
782/936 Doc ID 16912 Rev 5
30.2 Signal description
The PIT module has no external pins.
30.3 Memory map and registers description
This section provides a detailed description of all registers accessible in the PIT module.
30.3.1 Memory map
Table 417 gives an overview on all PIT registers.
Table 417. PIT memory map
Offset from
PIT_BASE
(0xC3FF_0000)
Register Location
0x0000 PITMCR—PIT Module Control Register on page 30-783
0x0004–0x00FF Reserved
Timer Channel 0
0x0100 LDVAL0—Timer 0 Load Value Register on page 30-784
0x0104 CVAL0—Timer 0 Current Value Register on page 30-785
0x0108 TCTRL0—Timer 0 Control Register on page 30-786
0x010C TFLG0—Timer 0 Flag Register on page 30-787
Timer Channel 1
0x0110 LDVAL1—Timer 1 Load Value Register on page 30-784
0x0114 CVAL1—Timer 1 Current Value Register on page 30-785
0x0118 TCTRL1—Timer 1 Control Register on page 30-786
0x011C TFLG1—Timer 1 Flag Register on page 30-787
Timer Channel 2
0x0120 LDVAL2—Timer 2 Load Value Register on page 30-784
0x0124 CVAL2—Timer 2 Current Value Register on page 30-785
0x0128 TCTRL2—Timer 2 Control Register on page 30-786
0x012C TFLG2—Timer 2 Flag Register on page 30-787
Timer Channel 3
0x0130 LDVAL3—Timer 3 Load Value Register on page 30-784
0x0134 CVAL3—Timer 3 Current Value Register on page 30-785
0x0138 TCTRL3—Timer 3 Control Register on page 30-786
0x013C TFLG3—Timer 3 Flag Register on page 30-787
0x0140–0x3FFF Reserved
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