Enhanced Direct Memory Access (eDMA) RM0046
412/936 Doc ID 16912 Rev 5
particular, this metric also reflects the time required to activate the channel. The eDMA
design supports the following hardware service request sequence:
● Cycle 1: eDMA peripheral request is asserted.
● Cycle 2: The eDMA peripheral request is registered locally in the eDMA module and
qualified. (TCD.START bit initiated requests start at this point with the registering of the
slave write to TCD bit 255).
● Cycle 3: Channel arbitration begins.
● Cycle 4: Channel arbitration completes. The transfer control descriptor local memory
read is initiated.
● Cycle 5–6: The first two parts of the activated channel’s TCD is read from the local
memory. The memory width to the eDMA engine is 64 bits, so the entire descriptor can
be accessed in four cycles.
● Cycle 7: The first system bus read cycle is initiated, as the third part of the channel’s
TCD is read from the local memory. Depending on the state of the crossbar switch,
arbitration at the system bus can insert an additional cycle of delay here.
● Cycle 8 – n: The last part of the TCD is read in. This cycle represents the 1st data
phase for the read, and the address phase for the destination write.
The exact timing from this point is a function of the response times for the channel’s read
and write accesses. In this case of an slave read and internal SRAM write, the combined
data phase time is 4 cycles. For an SRAM read and slave write, it is 5 cycles.
● Cycle n + 1: This cycle represents the data phase of the last destination write.
● Cycle n + 2: The eDMA engine completes the execution of the inner minor loop and
prepares to write back the required TCDn fields into the local memory. The
control/status fields at word offset 0x1C in TCDn are read. If the major loop is
complete, the MAJOR.E_LINK and E_SG bits are checked and processed if enabled.
● Cycle n + 3: The appropriate fields in the first part of the TCDn are written back into the
local memory.
● Cycle n + 4: The fields in the second part of the TCDn are written back into the local
memory. This cycle coincides with the next channel arbitration cycle start.
● Cycle n + 5: The next channel to be activated performs the read of the first part of its
TCD from the local memory. This is equivalent to Cycle 4 for the first channel’s service
request.
Assuming zero wait states on the system bus, DMA requests can be processed every 9
cycles. Assuming an average of the access times associated with slave-to-SRAM (4 cycles)
and SRAM-to-slave (5 cycles), DMA requests can be processed every 11.5 cycles
(4 + (4 + 5)/2 + 3). This is the time from Cycle 4 to Cycle “n 5.” The resulting peak request
rate, as a function of the system frequency, is shown in Tabl e 19 5 . This metric represents
millions of requests per second.
Table 195. eDMA peak request Rate (MReq/sec)
System Frequency
(MHz)
Request Rate
(Zero Wait States)
Request Rate
(with Wait States)
66.6 7.4 5.8
83.3 9.2 7.2
100.0 11.1 8.7
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