ST SPC560P34 - Cyclic Redundancy Check (CRC)

Cyclic Redundancy Check (CRC) RM0046
796/936 Doc ID 16912 Rev 5
32 Cyclic Redundancy Check (CRC)
32.1 Introduction
The Cyclic Redundancy Check (CRC) computing unit is dedicated to the computation of
CRC, thus off-loading the CPU. The SPC560P40/34 CRC supports two contexts. Each
context has a separate CRC computation engine in order to allow the concurrent
computation of the CRC of multiple data streams. The CRC computation is performed at
speed without wait states insertion. Bit-swap and bit-inversion operations can be applied on
the final CRC signature. Each context can be configured with one of two hard-wired
polynomials, normally used for most of the standard communication protocols. The data
stream supports multiple data width (byte/half-word/word) formats.
32.1.1 Glossary
● CRC: cyclic redundancy check
● CPU: central processing unit
● DMA: direct memory access
● CCITT: ITU-T (for Telecommunication Standardization Sector of the International
Telecommunications Union)
● SW: software
● WS: wait state
● SPI: serial peripheral interface
32.2 Main features
● 2 contexts for the concurrent CRC computation
● Separate CRC engine for each context
● Zero-wait states during the CRC computation (pipeline scheme)
● 2 hard-wired polynomials (CRC-16-CCITT and CRC-32 ethernet)
● Support for byte/half-word/word width of the input data stream
32.2.1 Standard features
● IPS bus interface
● CRC-16-CCITT
● CRC-32 ethernet
32.3 Block diagram
Figure 470 shows the top level diagram of the CRC unit.