Flash Memory RM0046
318/936 Doc ID 16912 Rev 5
17.2.13 Flash error response operation
The Flash array may signal an error response by asserting bkn_fl_xfr_err to terminate a
requested access with an error. This may occur due to an uncorrectable ECC error, or
because of improper sequencing during program/erase operations. When an error response
is received, the platform Flash controller does not update or validate a bank0 page read
buffer nor the bank1 temporary holding register. An error response may be signaled on read
or write operations. For more information on the specifics related to signaling of errors,
including Flash ECC, refer to subsequent sections in this chapter. For additional information
on the system registers that capture the faulting address, attributes, data and ECC
information, see 15, “Error Correction Status Module (ECSM).
17.2.14 Bank0 page read buffers and prefetch operation
The logic associated with bank0 of the platform Flash controller contains four 128-bit page
read buffers that hold data read from the Flash array. Each buffer operates independently,
and is filled using a single array access. The buffers are used for both prefetch and normal
demand fetches.
The organization of each page buffer is described as follows in a pseudo-code
representation. The hardware structure includes the buffer address and valid bit, along with
128 bits of page read data and several error flags.
struct { // bk0_page_buffer
reg addr[23:4];// page address
reg valid; // valid bit
reg rdata[127:0];// page read data
reg xfr_error; // transfer error indicator from Flash array
reg multi_ecc_error;// multi-bit ECC error indicator from Flash array
reg single_ecc_error;// single-bit correctable ECC indicator from
Flash array
} bk0_page_buffer[4];
For the general case, a page buffer is written at the completion of an error-free Flash access
and the valid bit asserted. Subsequent Flash accesses that “hit” the buffer, that is, the
current access address matches the address stored in the buffer, can be serviced in 0 AHB
wait states as the stored read data is routed from the given page buffer back to the
requesting bus master.
As noted in Section 17.2.13, “Flash error response operation a page buffer is not marked as
valid if the Flash array access terminated with any type of transfer error. However, the result
is that Flash array accesses that are tagged with a single-bit correctable ECC event are
loaded into the page buffer and validated. For additional comments on this topic, see
Section , “Buffer invalidation.
Prefetch triggering is controllable on a per-master and access-type basis. Bus masters may
be enabled or disabled from triggering prefetches, and triggering may be further restricted
based on whether a read access is for instruction or data. A read access to the platform
Flash controller may trigger a prefetch to the next sequential page of array data on the first
idle cycle following the request. The access address is incremented to the next-higher 16-
byte boundary, and a Flash array prefetch is initiated if the data is not already resident in a
page buffer. Prefetched data is always loaded into the least-recently-used buffer.
Buffers may be in one of six states, listed here in prioritized order:
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