LIN Controller (LINFlex) RM0046
500/936 Doc ID 16912 Rev 5
LIN error status register (LINESR)
HRF
Header Reception Flag
This bit is set by hardware and indicates a valid header reception is completed.
This bit must be cleared by software.
This bit is reset by hardware in Initialization mode and at end of completed or aborted frame.
Note: If filters are enabled, this bit is set only when identifier software filtering is
required, that is to say:–All filters are inactive and BF bit in LINCR1 is set
– No match in any filter and BF bit in LINCR1 is set
– TX filter match
Table 239. LINSR field descriptions (continued)
Field Description
Figure 238. LIN error status register (LINESR)
Offset: 0x000C Access: User read/write
0123456789101112131415
R 0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SZF OCF BEF CEF
SFEF
BDEF
IDPEF
FEF BOF 0 0 0 000NF
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset0000000000000000
Table 240. LINESR field descriptions
Field Description
SZF
Stuck at Zero Flag
This bit is set by hardware when the bus is dominant for more than a 100-bit time. If the dominant
state continues, SZF flag is set again after 87-bit time. It is cleared by software.
OCF
Output Compare Flag
0 No output compare event occurred
1 The content of the counter has matched the content of OC1[0:7] or OC2[0:7] in LINOCR. If this
bit is set and IOT bit in LINTCSR is set, LINFlex moves to Idle state.
If LTOM bit in LINTCSR is set, then OCF is cleared by hardware in Initialization mode. If LTOM bit is
cleared, then OCF maintains its status whatever the mode is.
BEF
Bit Error Flag
This bit is set by hardware and indicates to the software that LINFlex has detected a bit error. This
error can occur during response field transmission (Slave and Master modes) or during header
transmission (in Master mode).
This bit is cleared by software.
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