Figure 3. Block diagram (SPC560P40 full-featured configuration)
SRAM
(with ECC)
Slave SlaveSlave
Code Flash
(with ECC)
Data Flash
(with ECC)
PIT
STM
SWT
MC_RGM
MC_CGM
MC_ME
BAM
SIUL
WKPU
CRC
ECSM
e200z0 Core
32-bit
general
purpose
registers
Special
purpose
registers
Integer
execution
unit
Exception
handler
Variable
length
encoded
instructions
Instruction
unit
Load/store
unit
Branch
prediction
unit
JTAG
1.2 V regulator
control
XOSC
16 MHz
RC oscillator
FMPLL_0
(System)
Nexus port
controller
Interrupt
controller
eDMA
16 channels
Master
Master
Instruction
32-bit
Master
Data
32-bit
Crossbar switch (XBAR, AMBA 2.0 v6 AHB)
Peripheral bridge
FCU
Legend:
ADC Analog-to-digital converter
BAM Boot assist module
CRC Cyclic redundancy check
CTU Cross triggering unit
DSPI Deserial serial peripheral interface
ECSM Error correction status module
eDMA Enhanced direct memory access
eTimer Enhanced timer
FCU Fault collection unit
Flash Flash memory
FlexCAN Controller area network
FlexPWM Flexible pulse width modulation
FMPLL Frequency-modulated phase-locked loop
INTC Interrupt controller
JTAG JTAG controller
LINFlex Serial communication interface (LIN support)
MC_CGM Clock generation module
MC_ME Mode entry module
MC_PCU Power control unit
MC_RGM Reset generation module
PIT Periodic interrupt timer
SIUL System Integration unit Lite
SRAM Static random-access memory
SSCM System status and configuration module
STM System timer module
SWT Software watchdog timer
WKPU Wakeup unit
XOSC External oscillator
XBAR Crossbar switch
External ballast
Nexus 1
eDMA
16 channels
FlexPWM
CTU
3×
eTimer
DSPI
2×
FlexCAN
LINFlex
Safety port
ADC
(6 ch)
SSCM
(10 bit, 16 ch)
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