ST SPC560P34 - Figure 197. Example of Multiple Loop Iterations

RM0046 Enhanced Direct Memory Access (eDMA)
Doc ID 16912 Rev 5 415/936
Figure 197 shows how each DMA request initiates one minor loop transfer (iteration) without
CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor
loop DMA preemption is allowed. The number of minor loops in a major loop is specified by
the beginning iteration count (biter).
Figure 197. Example of multiple loop iterations
Figure 198 lists the memory array terms and how the TCD settings interrelate.
INT_HALF Control bit to enable interrupt when major loop is half complete
INT_MAJ Control bit to enable interrupt when major loop completes
Table 196. TCD primary control and status fields (continued)
TCD Field
Name
Description
DMA Request
Minor Loop 3
Current Major Loop
Iteration Count
(CITER)
Example Memory Array
•
•
•
DMA Request
Minor Loop 2
•
•
•
DMA Request
Minor Loop 1
•
•
•
Major Loop