Deserial Serial Peripheral Interface (DSPI) RM0046
480/936 Doc ID 16912 Rev 5
20.9 Initialization and application information
20.9.1 Managing queues
DSPI queues are not part of the DSPI module, but the DSPI includes features in support of
queue management. Queues are primarily supported in SPI configuration. This section
presents an example of how to manage queues for the DSPI.
1. The last command word from a queue is executed. The EOQ bit in the command word
is set to indicate to the DSPI that this is the last entry in the queue.
2. At the end of the transfer, corresponding to the command word with EOQ set is
sampled, the EOQ flag (EOQF) in the DSPIx_SR is set.
3. The setting of the EOQF flag disables both serial transmission, and serial reception of
data, putting the DSPI in the STOPPED state. The TXRXS bit is negated to indicate the
STOPPED state.
4. The eDMA continues to fill TX FIFO until it is full or step 5 occurs.
5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel
assigned to TX FIFO and RX FIFO. This is done by clearing the corresponding DMA
enable request bits in the eDMA controller.
6. Ensure all received data in RX FIFO has been transferred to memory receive queue by
reading the RXCNT in DSPIx_SR or by checking RFDF in the DSPIx_SR after each
read operation of the DSPIx_POPR.
7. Modify DMA descriptor of TX and RX channels for “new” queues.
8. Flush TX FIFO by writing a 1 to the CLR_TXF bit in the DSPIx_MCR register and flush
the RX FIFO by writing a 1 to the CLR_RXF bit in the DSPIx_MCR register.
9. Clear transfer count either by setting CTCNT bit in the command word of the first entry
in the new queue or via CPU writing directly to SPI_TCNT field in the DSPIx_TCR.
10. Enable DMA channel by enabling the DMA enable request for the DMA channel
assigned to the DSPI TX FIFO, and RX FIFO by setting the corresponding DMA set
enable request bit.
11. Enable serial transmission and serial reception of data by clearing the EOQF bit.
20.9.2 Baud rate settings
Table 230 shows the baud rate that is generated based on the combination of the baud rate
prescaler PBR and the baud rate scaler BR in the DSPIx_CTARs. The values are calculated
at a 100 MHz system frequency.
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