ST SPC560P34 - Boundary Scan

IEEE 1149.1 Test Access Port Controller (JTAGC) RM0046
850/936 Doc ID 16912 Rev 5
IDCODE instruction
IDCODE selects the 32-bit device identification register as the shift path between TDI and
TDO. This instruction allows interrogation of the MCU to determine its version number and
other part identification data. IDCODE is the instruction placed into the instruction register
when the JTAGC is reset.
SAMPLE instruction
The SAMPLE instruction obtains a sample of the system data and control signals present at
the MCU input pins and just before the boundary scan register cells at the output pins. This
sampling occurs on the rising edge of TCK in the capture-DR state when the SAMPLE
instruction is active. The sampled data is viewed by shifting it through the boundary scan
register to the TDO output during the Shift-DR state. There is no defined action in the
update-DR state. Both the data capture and the shift operation are transparent to system
operation.
SAMPLE/PRELOAD instruction
The SAMPLE/PRELOAD instruction has two functions:
● The SAMPLE part of the instruction samples the system data and control signals on
the MCU input pins and just before the boundary scan register cells at the output pins.
This sampling occurs on the rising-edge of TCK in the capture-DR state when the
SAMPLE/PRELOAD instruction is active. The sampled data is viewed by shifting it
through the boundary scan register to the TDO output during the shift-DR state. Both
the data capture and the shift operation are transparent to system operation.
● The PRELOAD part of the instruction initializes the boundary scan register cells before
selecting the EXTEST or CLAMP instructions to perform boundary scan tests. This is
achieved by shifting in initialization data to the boundary scan register during the shift-
DR state. The initialization data is transferred to the parallel outputs of the boundary
scan register cells on the falling edge of TCK in the update-DR state. The data is
applied to the external output pins by the EXTEST or CLAMP instruction. System
operation is not affected.
35.8.5 Boundary scan
The boundary scan technique allows signals at component boundaries to be controlled and
observed through the shift-register stage associated with each pad. Each stage is part of a
larger boundary scan register cell, and cells for each pad are interconnected serially to form
a shift-register chain around the border of the design. The boundary scan register consists
of this shift-register chain, and is connected between TDI and TDO when the EXTEST,
SAMPLE, or SAMPLE/PRELOAD instructions are loaded. The shift-register chain contains
a serial input and serial output, as well as clock and control signals.
35.9 e200z0 OnCE controller
The e200z0 core OnCE controller supports a complete set of Nexus 1 debug. A complete
discussion of the e200z0 OnCE debug features is available in the core reference manual.
35.9.1 e200z0 OnCE controller block diagram
Figure 502 is a block diagram of the e200z0 OnCE block.