ST SPC560P34 - Register Descriptions; Table 55. Power Domain Status Register (PCU_PSTAT) Field Descriptions; Figure 67. Power Domain Status Register (PCU_PSTAT)

Power Control Unit (MC_PCU) RM0046
186/936 Doc ID 16912 Rev 5
7.3.2 Register Descriptions
All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes
are ordered according to big endian. For example, the PD0 field of the PCU_PSTAT register
may be accessed as a word at address 0xC3FE_8040, as a half-word at address
0xC3FE_8042, or as a byte at address 0xC3FE_8043.
Power Domain Status Register (PCU_PSTAT)
This register reflects the power status of all available power domains.
Figure 67. Power Domain Status Register (PCU_PSTAT)
Address 0xC3FE_8040 Access: User read, Supervisor read, Test read
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000000000000
PD0
W
Reset0000000000000001
Table 55. Power Domain Status Register (PCU_PSTAT) Field Descriptions
Field Description
PDn
Power status for power domain #n
0Power domain is inoperable
1Power domain is operable