ST SPC560P34 - Figure 457. PIT Module Control Register (PITMCR); Registers Description; Table 418. PITMCR Field Descriptions

RM0046 Periodic Interrupt Timer (PIT)
Doc ID 16912 Rev 5 783/936
Note: Reserved registers read as 0. Writes have no effect.
30.3.2 Registers description
This section describes in address order all the PIT registers and their individual bits. PIT
registers are accessible only when the core is in supervisor mode (see Section 15.4.3,
“ECSM_reg_protection).
PIT Module Control Register (PITMCR)
This register controls whether the timer clocks are enabled and whether the timers run in
debug mode.
Figure 457. PIT Module Control Register (PITMCR)
Address: Base + 0x0000 Access: User read/write
0123456789101112131415
R00000000 00000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 00000 000 0
MDIS FRZ
W
Reset0000000000000010
Table 418. PITMCR field descriptions
Field Description
MDIS
Module Disable
Used to disable the module clock. This bit should be enabled before any other setup is done.
0: Clock for PIT Timers is enabled
1: Clock for PIT Timers is disabled (default)
FRZ
Freeze
Allows the timers to be stopped when the device enters debug mode.
0: Timers continue to run in debug mode.
1: Timers are stopped in debug mode.